The complexity encountered in designing integrated circuits (ICs) increases greatly as the functional count of the IC increases. For example, in synthesis practice of very large scale integration (VLSI) designs, verification and testing problems play a major role in the final stages of development and designing. Special difficulty may lie in the testing of netlists and chips with complex sequential behavior, such as those found in search engines of different natures. For instance, data communications are most often accomplished by sending a group of data in a packet, together with the address of the location for which the data are intended. A search for data may be accomplished by conducting a binary search based on the address or prefix where the data are retained, or stored. The search may be conducted by a lookup procedure that matches the query address with the stored address. Therefore, a search engine that enables the search of the data needs to demonstrate such capabilities in a manner consistent with the contemplated usage of the search engine.
One of the practical methods to prove that search engines may function well in real chip practice is to perform their all-round verification by means of sequential testers that simulate actual usage of such search engines.
Longest prefix search engines (LPSEs) may be more difficult for simulation and testing than search engines for perfect match type, because for LPSEs one need simulate engine commands dealing with address prefixes of an arbitrary length rather than addresses of a fixed length. Moreover, LPSEs require particular encoding/decoding of engine internal memory, which may be significantly different from what is required for search engines for perfect match types.
Thus, it would be desirable to provide a sequential and functional tester which may be employed for simulating and testing LPSEs.